Testing of signal integrity (SI) in current high-speed\udICs, requires automatic test equipment test resources at the multigigahertz\udrange, normally not available. Furthermore, for most internal\udnets of state-of-the-art ICs, external speed testing is not possible\udfor the newest technologies. In this paper, on-chip testing for\udSI faults in digital interconnect signals, using built-in high speed\udmonitors, is proposed. A coherent sampling scheme is used to capture\udthe signal information. Two monitors to test SI violations are\udproposed: one for undershoots at the high logic level and the other\udfor overshoots at the low logic level. The monitors are capable of\uddetecting small noise pulses and have been extended to test sequentially\udmore than one signal. The cost of the proposed strategy is\udanalyzed in terms of area, delay penalization, and test time. The\udeffects of clock jitter and process variations are analyzed. Experimental\udresults obtained in designed and fabricated circuits show\udthe feasibility of the proposed testing strategy. A good agreement\udappears between the theoretical analysis, simulation results, and\udthe experimental measurements.
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